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DATA SHEET
MOS INTEGRATED CIRCUIT
PD17P228
4-BIT SINGLE-CHIP MICROCONTROLLER FOR SMALL GENERAL-PURPOSE INFRARED REMOTE CONTROLLER
DESCRIPTION
The PD17P228 is a model of the PD17228 with a one-time PROM instead of an internal mask ROM. Since the user can write programs to the PD17P228, it is ideal for experimental production or small-scale production of the PD17225, 17226, 17227 or 17228 systems. When reading this document, also read the documents related to the PD17225, 17226, 17227 and 17228. Detailed functions are described in the following user's manual. Read this manual when designing your system.
PD172xx Series User's Manual: U12795E
FEATURES
* Pin compatible with PD17225, 17226, 17227 and 17228 (except PROM programming function) * Carrier generator circuit for infrared remote controller (REM output) * 17K architecture: General-purpose register method * Program memory (one-time PROM): 16 Kbytes (8192 x 16) * Data memory (RAM): 223 x 4 bits * Pull-up resistor can be connected to RESET pin * Low-voltage detection circuit (WDOUT output) * Supply voltage: VDD = 2.2 to 3.6 V (fx = 4 MHz: high-speed mode, 4 s) VDD = 3.0 to 3.6 V (fx = 8 MHz: high-speed mode, 2 s)
APPLICATIONS
Preset remote controllers, toys, and portable systems
ORDERING INFORMATION
Part Number Package 30-pin plastic SSOP (7.62 mm (300))
PD17P228MC-5A4
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U14542EJ1V0DS00 (1st edition) Date Published April 2000 N CP(K) Printed in Japan
(c)
2000
PD17P228
PIN CONFIGURATION (TOP VIEW)
* 30-pin plastic SSOP (7.62 mm (300))
PD17P228MC-5A4
(1) Normal oprating mode
P0D2 P0D3 INT P0E0 P0E1 P0E2 P0E3 REM VDD XOUT XIN GND RESET WDOUT IC1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IC2 P0D1 P0D0 P0C3 P0C2 P0C1 P0C0 P0B3 P0B2 P0B1 P0B0 P0A3 P0A2 P0A1 P0A0
GND IC1, IC2 INT
: Ground : Internally connected
Note
: External interrupt request signal input
P0A0-P0A3 : Input port (CMOS input) P0B0-P0B3 : Input port (CMOS input) P0C0-P0C3 : Output port (N-ch open-drain output) P0D0-P0D3 : Output port (N-ch open-drain output) P0E0-P0E3 : I/O port (CMOS push-pull output) REM RESET VDD WDOUT XIN, XOUT Note : Remote controller output (CMOS push-pull output) : Reset input : Power supply : Hang-up/low voltage detection output (N-ch open-drain output) : Resonator connection
This pin cannot be used. Leave unconnected.
2
Data Sheet U14542EJ1V0DS00
PD17P228
(2) PROM programming mode
D2 D3 VPP
1 2 3 4 5
30 29 28 27 26 25 24 23 22 21 20 19 18
(Open) D1 D0 D7 D6 D5 D4 MD3 MD2 MD1 MD0
(L) 6 7 (Open) VDD (Open) CLK GND (L) (Open) (Open) 8 9 10 11 12 13 14 15
(L) 17 16
Caution Contents in parantheses indicate how to handle unused pins in PROM programming mode. L :Connect to GND via a resistor (470 ) separately. OPEN:Leave unconnected. CLK D0 - D7 GND VDD VPP : Clock input for PROM : Data input/output for PROM : Ground : Power supply : Power supply for PROM writing
MD0 - MD3 : Mode select input for PROM
Data Sheet U14542EJ1V0DS00
3
PD17P228
BLOCK DIAGRAM
P0A0 P0A1 P0A2 P0A3
P0A
RF RAM 223 x 4 bits
Remote Control Divider
REM
8-bit timer
P0B0 (MD0) P0B1 (MD1) P0B2 (MD2) P0B3 (MD3)
P0B
SYSTEM REG. Interrupt Controller ALU INT (VPP)
P0C0 (D4) P0C1 (D5) P0C2 (D6) P0C3 (D7)
P0C
One Time PROM 8192 x 16 bits P0D0 (D0) P0D1 (D1) P0D2 (D2) P0D3 (D3) P0D
Instruction Decoder
RESET WDOUT Program Counter
P0E0 P0E1 P0E2 P0E3
P0E Stack (5 levels)
Power Supply Circuit CPU Clock
VDD GND
Basic Interval/ Watchdog Timer
XIN (CLK) OSC XOUT
Remark
( ): during PROM programming mode
4
Data Sheet U14542EJ1V0DS00
PD17P228
CONTENTS 1. DIFFRENCES AMONG PD17225, 17226, 17227, 17228 AND PD17P228 .......................... 6
2.
PIN FUNCTIONS ..........................................................................................................................
2.1 2.2 2.3 2.4 2.5 Normal Operation Mode .................................................................................................................... PROM Programming Mode ............................................................................................................... Input/Output Circuits ......................................................................................................................... Processing of Unused Pins .............................................................................................................. Notes on Using the RESET and INT Pins ........................................................................................
7
7 8 9 10 10
3.
WRITING AND VERIFYING ONE-TIME PROM (PROGRAM MEMORY) ..............................
3.1 3.2 3.3 Operating Mode When Writing/Verifying Program Memory .......................................................... Program Memory Writing Procedure ............................................................................................... Program Memory Reading Procedure .............................................................................................
11
11 12 13
4.
ELECTRICAL SPECIFICATIONS ................................................................................................
14
5.
PACKAGE DRAWING .................................................................................................................
21
6.
RECOMMENDED SOLDERING CONDITIONS ..........................................................................
22
APPENDIX. DEVELOPMENT TOOLS ...............................................................................................
23
Data Sheet U14542EJ1V0DS00
5
PD17P228
1. DIFFERENCES AMONG PD17225, 17226, 17227, 17228 AND PD17P228
PD17P228 is equipped with PROM to which data can be written by the user instead of the internal mask ROM
(program memory) of the PD17228. Table 1-1 shows the differences between the PD17225, 17226, 17227, 17228 and PD17P228. The differences among these five models are the program memory and mask option, and their CPU functions and internal hardware are identical. Therefore, the PD17P228 can be used to evaluate the program developed for the
PD17225, 17226, 17227, and 17228 system. Note, however, that some of the electrical specifications such
as supply current and low-voltage detection voltage of the PD17P228 are different from those of the
PD17225, 17226, 17227, and 17228.
Table 1-1. Differences among PD17225, 17226, 17227, 17228 and PD17P228
Product Name Item Program memory One-time PROM 16 K bytes (8192 x 16) (0000H-1FFFH) Data memory Pull-up resistor of RESET Pin Low-voltage detector circuit
Note
PD17P228
PD17225
PD17226
PD17227
PD17228
Mask ROM 4 K bytes (2048 x 16) (0000H-07FFH) 8 K bytes (4096 x 16) (0000H-0FFFH) 12 K bytes (6144 x 16) (0000H-17FFH) 16 K bytes (8192 x 16) (0000H-1FFFH)
223 x 4 bits Provided Provided Provided 2 s (VDD = 3.0 to 3.6 V) 4 s (VDD = 2.2 to 3.6 V) 16 s (VDD = 2.2 to 3.6 V)
111 x 4 bits Any (mask option) Any (mask option) Not provided 2 s (VDD = 2.2 to 3.6 V) 4 s (VDD = 2.0 to 3.6 V)
223 x 4 bits
VPP pin, operation mode select pin Instruction execution time (tCY)
Operation when P0C, P0D are standby Supply voltage Package VDD = 2.0 to 3.6 V
30-pin plastic SSOP (7.62 mm (300))
Retain output level immediately before standby mode VDD = 2.0 to 3.6 V
* 28-pin plastic SOP (9.53 mm (375)) * 28-pin plastic SDIP (10.16 mm (400)) * 30-pin plastic SSOP (7.62 mm (300))
Note
Although the circuit configuration is identical, its electrical characteristics differ depending on the product.
6
Data Sheet U14542EJ1V0DS00
PD17P228
2. PIN FUNCTIONS
2.1 Normal Operation Mode
Pin No. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 1 2 4 5 6 7 Symbol P0A0 P0A1 P0A2 P0A3 P0B0 P0B1 P0B2 P0B3 P0C0 P0C1 P0C2 P0C3 P0D0 P0D1 P0D2 P0D3 P0E0 P0E1 P0E2 P0E3 Function 4-bit CMOS input port with pull-up resistor. Can be used for key return input of key matrix. When at least one of these pins goes low, standby function is released. Output Format At Reset
-
Input
4-bit CMOS input port with pull-up resistor. Can be used for key return input of key matrix. When at least one of these pins goes low, standby function is released.
-
Input
4-bit N-ch open-drain output port. Can be used for key source output of key matrix.
N-ch open-drain
Low-level output
4-bit N-ch open-drain output port. Can be used for key source output of key matrix.
N-ch open-drain
Low-level output
4-bit input/output port. Can be set in input or output mode in 1-bit units. In output mode, this port functions as a high current CMOS output port. In input mode, function as CMOS input and can be specified to connect pull-up resistor by program. Outputs transfer signal for infrared remote controller. Active-high output. System reset input. CPU can be reset when low-level signal is input to this pin. While low-level signal is input, oscillator is stopped. This pin connected to pull-up resistor by mask option. Power supply Ground External interrupt request signal input Output detecting hang-up and drop in supply voltage. This pin outputs at low level either when an overflow occurs in the watchdog timer, when an overflow/underflow occurs in the stack, or when the supply voltage drops below a specified level. Connect this pin to the RESET pin. Connects ceramic resonator for system clock oscillation These pins cannot be used. Leave open.
CMOS push-pull
Input
8
REM
CMOS push-pull
Low-level output
13
RESET
-
Input
9 12 3
VDD GND INT
- - -
- - Input Highimpedance Low-level output at low voltage detection (Oscillation stops) -
14
WDOUT
N-ch open-drain
11 10 15 30
XIN XOUT IC1 IC2
-
-
Data Sheet U14542EJ1V0DS00
7
PD17P228
2.2 PROM Programming Mode
Pin No. 3 Symbol VPP Function Power supply for PROM programming. Apply +12.5 V to this pin as the program voltage when writing/ verifying program memory. Power supply. Apply +6 V to this pin when writing/verifying program memory. Inputs clock for PROM programming. Ground. Input pins used to select operation mode when PROM is programmed. Output Format At Reset
-
-
9
VDD
- - - -
- - - Input
11 12 20 23 24 27 28 29 1 2
CLK GND MD0 MD3 D4 D7 D0 D1 D2 D3
Input/output 8-bit data for PROM programming
CMOS push-pull
Input
Remark
The other pins are not used in the PROM programming mode. How to handle the other opins are described in the section PIN CONFIGURATION (2) PROM programming mode.
8
Data Sheet U14542EJ1V0DS00
PD17P228
2.3 Input/Output Circuits
The equivalent input/output circuit for each PD17P228 pin is shown below. (1) P0A, P0B (4) RESET
VDD
VDD (Mask option)
Input buffer
Input buffer
(2) P0C, P0D Schmitt trigger input with hysteresis characteristics
data Output latch N-ch
(5) INT
(3) P0E
VDD
Input buffer
data
Pull-up register VDD
P-ch
Schmitt trigger input with hysteresis characteristics
data
Output latch
P-ch
(6) REM
output disable N-ch
VDD data
Selector Input buffer
P-ch
output disable
N-ch
(7) WDOUT
data
N-ch
Data Sheet U14542EJ1V0DS00
9
PD17P228
2.4 Processing of Unused Pins
Process the unused pins as follows: Table 2-1. Processing of Unused Pins
Pin P0A0-P0A3 P0B0-P0B3 P0C0-P0C3 P0D0-P0D3 P0E0-P0E3 Connect to VDD. Connect to VDD. Connect to GND. Connect to GND. Input : Individually connect to VDD or GND via resistor. Output : Leave open. Leave open. Connect to GND. Connect to VDD via resistor. These pins cannot be used. Leave open. Recommended Connection
REM INT WDOUT IC1, IC2
2.5 Notes on Using the RESET and INT Pins
In addition to the functions shown in 2. PIN FUNCTION, the RESET pin also has the function of setting a test mode (for IC testing) in which the internal operations of the PD17P228 are tested. When a voltage higher than VDD is applied to either of these pins, the test mode is set. This means that, even during normal operation, the PD17P228 may be set in the test mode if noise exceeding VDD is applied. For example, if the wiring length of the RESET or INT pin is too long, noise superimposed on the wiring line of the pin may cause the above problem. Therefore, keep the wiring length of these pins as short as possible to suppress the noise; otherwise, take noise preventive measures as shown below by using external components. * Connect diode with low VF between VDD and RESET/INT pin
VDD
* Connect capacitor between VDD and RESET/INT pin
VDD
Diode with low VF RESET, INT
VDD RESET, INT
VDD
Connect the WDOUT and RESET pins since a low level is output after the test mode is set using the INT pin.
10
Data Sheet U14542EJ1V0DS00
PD17P228
3. WRITING AND VERIFYING ONE-TIME PROM (PROGRAM MEMORY)
The program memory of the PD17P228 is a one-time PROM of 8192 x 16 bits. To write or verify this one-time PROM, the pins shown in Table 3-1 are used. Note that no address input pin is used. Instead, the address is updated by using the clock input from the CLK pin. Table 3-1. Pins Used to Write/Verify Program Memory
Pin Name VPP VDD CLK MD0-MD3 D0-D7 Function Supplies voltage when writing/verifying program memory. Apply +12.5 V to this pin. Power supply. Supply +6 V to this pin when writing/verifying program memory. Inputs clock to update address when writing/verifying program memory. By inputting pulse four times to CLK pin, address of program memory is updated. Input to select operation mode when writing/verifying program memory. Inputs/outputs 8-bit data when writing/verifying program memory.
3.1 Operating Mode When Writing/Verifying Program Memory
The PD17P228 is set in the program memory write/verify mode when +6 V is applied to the VDD pin and +12.5 V is applied to the VPP pin after the PD17P228 has been in the reset status (VDD = 5 V, RESET = 0 V) for a specific time. In this mode, the operating modes shown in Table 3-2 can be set by setting the MD0 through MD3 pins. Leave all the pins other than those shown in Table 3-1 unconnected or connect them to GND via pull-down resistor (470 ). (Refer to PIN CONNECTION (2) PROM programming mode.) Table 3-2. Setting Operation Mode
Setting of Operating Mode VPP +12.5 V VDD +6 V MD0 H L L H MD1 L H L x MD2 H H H H MD3 L H H H Program memory address 0 clear mode Write mode Verify mode Program inhibit mode Operating Mode
x: don't care (L or H)
Data Sheet U14542EJ1V0DS00
11
PD17P228
3.2 Program Memory Writing Procedure
The program memory is written at high speed in the following procedure. (1) (2) (3) (4) (5) (6) (7) (8) (9) Pull down the pins not used to GND via resistor. Keep the CLK pin low. Supply 5 V to the VDD pin. Keep the VPP pin low. Supply 5 V to the VPP pin after waiting for 10 s. Set the program memory address 0 clear mode by using the mode setting pins. Supply +6 V to VDD and +12.5 V to VPP. Set the program inhibit mode. Write data to the program memory in the 1-ms write mode. Set the program inhibit mode. Set the verify mode. If the data have been written to the program memory, proceed to (10). If not, repeat steps (7) through (9). (10) Additional writing of (number of times of writing in (7) through (9): X) x 1 ms. (11) Set the program inhibit mode. (12) Input a pulse to the CLK pin four times to update the program memory address (+1). (13) Repeat steps (7) through (12) up to the last address. (14) Set the 0 clear mode of the program memory address. (15) Change the voltages on the VDD and VPP pins to 5 V. (16) Turn off power. The following figure illustrates steps (2) through (12) above.
Repeated X time Reset VPP VPP VDD GND VDD VDD+1 VDD GND CLK Write Verify Additional write Address increment
D0-D7
Hi-Z
Data input
Hi-Z
Data output
Hi-Z
Data input
Hi-Z
MD0
MD1
MD2
MD3
12
Data Sheet U14542EJ1V0DS00
PD17P228
3.3 Program Memory Reading Procedure
(1) (2) (3) (4) (5) (6) (7) (8) (9) Pull down the pins not used to GND via resistor. Keep the CLK pin low. Supply 5 V to the VDD pin. Keep the VPP pin low. Supply 5 V to the VPP pin after waiting for 10 s. Set the program memory address 0 clear mode by using the mode setting pins. Supply +6 V to VDD and +12.5 V to VPP. Set the program inhibit mode. Set the verify mode. Data of each address is output sequentially each time the clock pulse is input to the CLK pin four times. Set the program inhibit mode. Set the program memory address 0 clear mode.
(10) Change the voltage on the VDD and VPP pins to 5 V. (11) Turn off power. The following figure illustrates steps (2) through (9) above.
Reset VPP VPP VDD GND VDD+1 VDD GND CLK
VDD
D0-D7
Hi-Z
Data output
Data output
Hi-Z
MD0
MD1
"L"
MD2
MD3
Data Sheet U14542EJ1V0DS00
13
PD17P228
4. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25C)
Item Supply voltage PROM power supply Input voltage Output voltage High-level output current
Note
Symbol VDD VPP VI VO IOH REM pin
Conditions
Ratings -0.3 to +7.0 -0.3 to +13.5 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 Peak value rms value -36.0 -24.0 -7.5 -5.0 -22.5 -15.0 7.5 5.0 22.5 15.0 30.0 20.0 -40 to +85 -65 to +150
Unit V V V V mA mA mA mA mA mA mA mA mA mA mA mA C C mW
1 pin (P0E pin)
Peak value rms value
Total of P0E pins
Peak value rms value
Low-level output current
Note
IOL
1 pin (P0C, P0D, P0E, REM or WDOUT pin) Total of P0C, P0D, WDOUT pins Total of P0E pins
Peak value rms value Peak value rms value Peak value rms value
Operating temperature Storage temperature Power dissipation
TA Tstg Pd TA = 85C
180
Note
Calculate rms value by this expression: [rms value] = [Peak value] x Duty
Caution Even if one of the parameters exceeds its absolute maximum rating even momentarily, the quality of the product may be degraded. The absolute maximum rating therefore specifies the upper or lower limit of the value at which the product can be used without physical damages. Be sure not to exceed or fall below this value when using the product.
14
Data Sheet U14542EJ1V0DS00
PD17P228
Recommended Operating Ranges (TA = -40 to +85C, VDD = 2.2 to 3.6 V)
Item Supply voltage Symbol VDD1 fX = 1 MHz Conditions High-speed mode (Instruction execution time: 16 s) Ordinary mode (Instruction execution time: 4 s) High-speed mode (Instruction execution time: 4 s) High-speed mode (Instruction execution time: 2 s) 3.0 3.6 V MIN. 2.2 TYP. MAX. 3.6 Unit V
VDD2
fX = 4 MHz
VDD3
fX = 8 MHz
VDD4
Oscillation frequency Operating temperature Low-voltage detector circuit
Note
fX TA TCY
1.0 -40 4
4.0 +25
8.0 +85 32
MHz C
s
Note
Reset if the status of VDD = 2.05 V (TYP.) lasts for 1 ms or longer. Program hang-up does not occur even if the voltage drops, until the reset function is effected (when the RESET pin and WDOUT pin are connected). Some oscillators stop oscillating before the reset function is effected.
fX vs VDD
(MHZ) 10 9 8 7 6 5
System clock: fX (MHZ) (Normal mode)
4 3
Operation guaranteed area
2
1
0.4 0 2 2.2 3 3.6 4
Supply voltage: VDD (V)
Remark The region indicated by the broken line in the above figure is the guaranteed operating range in the highspeed mode.
Data Sheet U14542EJ1V0DS00
15
PD17P228
System Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 2.2 to 3.6 V)
Resonator Ceramic resonator Recommended Constants Item Oscillation frequency (fX)Note 1 Conditions MIN. 1.0 TYP. 4.0 MAX. 8.0 Unit MHz
XIN
XOUT
Oscillation Note 2 stabilization time
After VDD reached MIN. in oscillation voltage range
4
ms
Notes 1. The oscillation frequency only indicates the oscillator characteristics. 2. The oscillation stabilization time is necessary for oscillation to be stabilized, after VDD application or STOP mode release. Caution To use a system clock oscillator circuit, perform the wiring in the area enclosed by the dotted line in the above figure as follows, to avoid adverse wiring capacitance influences: * Keep wiring length as short as possible. * Do not cross a signal line with some other signal lines. Do not route the wiring in the vicinity of lines through which a large current flows. * Always keep the oscillator capacitor ground at the same potential as GND. Do not ground the capacitor to a ground pattern, through which a large current flows. * Do not extract signals from the oscillator. External circuit example
XIN
XOUT R1
C1
C2
Remark
To select a resonator and determine oscillator constants, please evaluate the oscillation yourself or request the resonator manufacturer to evaluate it.
16
Data Sheet U14542EJ1V0DS00
PD17P228
DC Characteristics (TA = -40 to +85C, VDD = 2.2 to 3.6 V)
Item High-level input voltage Symbol VIH1 VIH2 VIH3 Low-level input voltage VIL1 VIL2 VIL3 High-level input leakage current Low-level input leakage current High-level output leakage current Low-level output leakage current Internal pull-up resistor R1 R2 High-level output current High-level output voltage Low-level output voltage IOH1 VOH VOL1 P0E, RESET P0A, P0B REM P0E, REM P0C, P0D, REM, WDOUT P0E WDOUT = low level VOH = 1.0 V, VDD = 3 V IOH = -0.5 mA IOL = 0.5 mA 25 100 -6 VDD-0.3 0 50 200 -13 100 400 -24 VDD 0.3 k k mA V V ILIH RESET, INT P0A, P0B P0E RESET, INT P0A, P0B P0E P0A, P0B, P0E, RESET, INT INT P0E P0C, P0D, P0E, WDOUT P0E, WDOUT VIH = VDD Conditions MIN. 0.8VDD 0.7VDD 0.8VDD 0 0 0 TYP. MAX. VDD VDD VDD 0.2VDD 0.3VDD 0.35VDD 3 Unit V V V V V V
A A A A A
ILIL1 ILIL2 ILOH
VIL = 0 V VIL = 0 V w/o pull-up resistor VOH = VDD
-3 -3 3
ILOL
VOL = 0 V w/o pull-up resistor
-3
VOL2 Low-voltage detector circuit VDT
IOL = 1.5 mA VDT = VDD
0 2.05
0.3 2.2
V V
Data retention voltage Supply current
VDDDR IDD1
RESET = low level or STOP mode Operating mode (high-speed) VDD = 3 V 10% fX = 1 MHz fX = 4 MHz fX = 8 MHz
1.3 0.55 1.0 1.3 0.5 0.75 0.9 0.4 0.5 0.6 2.0 TA = 25 C 2.0
3.6 1.1 2.0 2.6 1.0 1.5 1.8 0.8 1.0 1.2 20.0 5.0
V mA mA mA mA mA mA mA mA mA
IDD2
Operating mode (low-speed)
VDD = 3 V 10%
fX = 1 MHz fX = 4 MHz fX = 8 MHz
IDD3
HALT mode
VDD = 3 V 10%
fX = 1 MHz fX = 4 MHz fX = 8 MHz
IDD4
STOP mode
VDD = 3 V 10% built-in POC
A A
Data Sheet U14542EJ1V0DS00
17
PD17P228
AC Characteristics (TA = -40 to +85C, VDD = 2.2 to 3.6 V)
Item CPU clock cycle time (instruction execution time) INT high/low level width RESET low level lwidth
Note
Symbol tCY1 tCY2 tINTH, tINTL tRSL VDD = 3.0 to 3.6 V
Conditions
MIN. 3.8 1.9 20 10
TYP.
MAX. 33 33
Unit
s s s s
Note
The CPU clock cycle time (instruction execution time) is determined by the oscillation frequency of the resonator connected and SYSCK (RF: address 02H) of the register file. The figure on the right shows the CPU clock cycle time tCY vs. supply voltage VDD characteristics.
CPU clock cycle time tcY (s)
tCY vs VDD
40 33
10 9 8 7 6 5 4 3 3.8 Operation guaranteed area
2
1.9
1 0 1
2.2 2 3
3.6 4
Supply voltage VDD (V)
18
Data Sheet U14542EJ1V0DS00
PD17P228
DC Programming Characteristics (TA = 25 C, VDD = 6.0 0.25 V, VPP = 12.5 0.3 V)
Parameter High-level input voltage Symbol VIH1 VIH2 Low-level input voltage VIL1 VIL2 Input leakage current High-level output voltage Low-level output voltage VDD supply current VPP supply current ILI VOH VOL IDD IPP MD0 = VIL, MD1 = VIH Test Conditions Other than CLK CLK Other than CLK CLK VIN = VIL or VIH IOH = -1 mA IOL = 1.6 mA VDD-1.0 0.4 30 30 MIN. 0.7 VDD VDD-0.5 0 0 TYP. MAX. VDD VDD 0.3 VDD 0.4 10 Unit V V V V
A
V V mA mA
Cautions 1. Keep VPP to within +13.5 V including overshoot. 2. Apply VDD before VPP and turns it off after VPP. AC Programming Characteristics (TA = 25C, VDD = 6.0 0.25 V, VPP = 12.5 0.3 V)
Parameter Address setup timeNote (vs. MD0) Symbol tAS tM1S tDS tAH tDH tDF tVPS tVDS tPW tOPW tMOS tDV tM1H tM1R tPCR tXH, tXL fX tI tM3S tM3H tM3SR tDAD tHAD tM3HR tDFR tRES
When program memory is read When program memory is read When program memory is read When program memory is read When program memory is read
Test Conditions
MIN. 2 2 2 2 2 0 2 2 0.95 0.95 2
TYP.
MAX.
Unit
s s s s s
130 ns
MD1 setup time (vs. MD0) Data setup time (vs. MD0) Address hold timeNote (vs. MD0) Data hold time (vs. MD0) MD0 data output float delay time VPP setup time (vs. MD3) VDD setup time (vs. MD3) Initial program pulse width Additional program pulse width MD0 setup time (vs. MD1) MD0 data output delay time MD1 hold time (vs. MD0) MD1 recovery time (vs. MD0) Program counter reset time CLK input high-, low-level width CLK input frequency Initial mode set time MD3 setup time (vs. MD1) MD3 hold time (vs. MD1) MD3 setup time (vs. MD0) AddressNote data output delay time Address
Note
s s
1.0 1.05 21.0 ms ms
s
1
MD0 = MD1 = VIL tM1H+tM1R 50 s 2 2 10 0.125
s s s s s
4.19 2 2 2 2 2 0 2 2 10 130
MHz
s s s s s
ns
data output hold time
MD3 hold time (vs. MD0) MD3 data output float delay time Reset setup time
s s s
Notes The internal address increment (+1) is performed on the fall of the 3rd clock, where 4 clocks compreise one cycle. The internal clock is not connected to a pin.
Data Sheet U14542EJ1V0DS00
19
PD17P228
Program Memory Write Timing
tRES tVPS VPP VDD VPP GND VDD+1 VDD VDD GND CLK Hi-Z tI MD0 tPW MD1 tPCR MD2 tM3S MD3 tM3H tM1S tM1H tM1R tMOS tOPW tXL Data input tDS tDH Data output tDV tDF Data input tDS tDH tAH tAS Data input
tVDS tXH
D0-D7
Program Memory Read Timing
tRES tVPS VPP VPP VDD GND VDD+1 VDD VDD GND CLK tXL tHAD D0-D7 tI MD0 tDV Data output Data output tM3HR tDFR tDAD tVDS tXH
MD1
"L" tPCR
MD2 tM3SR MD3
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Data Sheet U14542EJ1V0DS00
PD17P228
5. PACKAGE DRAWING
30-PIN PLASTIC SSOP (7.62 mm (300))
30 16 detail of lead end F G T
P 1 A 15 E
L U
H I J
S
C D M
M
N
S
B K
NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition.
ITEM A B C D E F G H I J K L M N P T U
MILLIMETERS 9.850.15 0.45 MAX. 0.65 (T.P.) 0.24 +0.08 -0.07 0.10.05 1.30.1 1.2 8.10.2 6.10.2 1.00.2 0.170.03 0.5 0.13 0.10 3 +5 -3 0.25 0.60.15 S30MC-65-5A4-2
Data Sheet U14542EJ1V0DS00
21
PD17P228
6. RECOMMENDED SOLDERING CONDITIONS
For the PD17P228 soldering must be performed under the following conditions. For details of recommended conditions for surface mounting, refer to information document "Semiconductor Device Mounting Technology Manual" (C10535E). For other soldering methods, please consult with NEC personnel. Table 6-1. Soldering Conditions of Surface Mount Type * PD17P228MC-5A4: 30-pin plastic SSOP (7.62 mm(300))
Soldering Method Infrated Reflow
Soldering Conditions Package peak temperature: 235C, Time: 30 seconds max. (210C min.), Number of times: 2 max. Number of days: 3 (after that, prebaking is necessary at 125C for 10 hours) Package peak temperature: 215C, Time: 40 seconds max. (200C min.), Number of times: 2 max. Number of days: 3 (after that, prebaking is necessary at 125C for 10 hours) Solder bath temperature: 260C max, Time: 10 seconds max., Number of times: once, preheating temperature: 120C max. (package surface temperature) Number of days: 3 (after that, prebaking is necessary at 125C for 10 hours) Pin temperature: 300C max., Time: 3 seconds max. (per side of device)
Symbol IR35-103-2
VPS
VP15-103-2
Wave soldering
WS-60-103-1
Partial heating
--
Note
Number of days in storage after the dry pack has been opened. The storage conditions are at 25C, 65% RH MAX.
Caution Do not use two or more soldering methods in combination (except the partial heating method).
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Data Sheet U14542EJ1V0DS00
PD17P228
APPENDIX. DEVELOPMENT TOOLS
To develop the programs for the PD17P228 subseries, the following development tools are available: Hardware
Name In-circuit emulator IE-17K, IE-17K-ETNote 1 Remarks IE-17K and IE-17K-ET are the in-circuit emulators used in common with the 17K series microcontroller. TM IE-17K and IE-17K-ET are connected to a PC-9800 series or IBM PC/AT compatible machines as the host machine with RS-232C. By using these in-circuit emulators with a system evaluation board corresponding to the microcomputer, the emulators can emulate the microcomputer. A higher level debugging TM environment can be provided by using man-machine interface SIMPLEHOST . This is an SE board for PD17225 subseries. It can be used alone to evaluate a system or in combination with an in-circuit emulator for debugging. EP-17K30GS is an emulation probe for 17K series 30-pin SSOP (MC-5A4). When used with EV-9500GT-30Note 2, it connects an SE board to the target system. The EV-9500GT-30 is a conversion adapter for the 30-pin SSOP (MC-5A4). It is used to connect the EP-17K30GS and target system. AF-9706, AF-9708, and AF-9709 are PROM programmers corresponding to PD17P228. By connecting program adapter PA-17P236 to this PROM programmer, PD17P228 can be programmed. PA-17P236 are adapters that is used to program PD17P228, and is used in combination with AF-9706, AF-9708, or AF-9709.
SE board (SE-17225) Emulation probe (EP-17K30GS) Conversion adapter Note 2 (EV-9500GT-30 ) PROM programmer Note 3 Note 3 (AF-9706 , AF-9708 , Note 3 AF-9709 ) Program adapter (PA-17P236)
Notes 1. Low-cost model: External power supply type 2. Two EV-9500GT-30 are supplied with the EP-17K30GS. Five EV-9500GT-30s are optionally available as a set. 3. These are products from Ando Electric Co., Ltd. For details, consult Ando Electric Co., Ltd. (Tel: 033733-1166).
Data Sheet U14542EJ1V0DS00
23
PD17P228
Software
Name 17K assembler (RA17K) Outline The RA17K is an assembler common to the 17K series products. When developing the program of devices, RA17K is used in combination with a device file (AS17225). Host Machine PC-9800 series IBM PC/AT compatible machine OS Japanese WindowsTM Supply 3.5" 2HD Order Code
SAA13RA17K SAB13RA17K SBB13RA17K
Japanese Windows
3.5" 2HC
English Windows
Device file (AS17225)
The AS17225 is a device file for PD17225, 17226, 17227, and 17228 and is used in combination with an assembler for the 17K series (RA17K).
PC-9800 series IBM PC/AT compatible machine
Japanese Windows
3.5" 2HD
SAA13AS17225 SAB13AS17225 SBB13AS17225
Japanese Windows
3.5" 2HC
English Windows
Support software (SIMPLEHOST)
SIMPLEHOST is a software package that enables man-machine interface on the Windows when a program is developed by using an incircuit emulator and a personal computer.
PC-9800 series IBM PC/AT compatible machine
Japanese Windows
3.5" 2HD
SAA13ID17K SAB13ID17K SBB13ID17K
Japanese Windows
3.5" 2HC
English Windows
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Data Sheet U14542EJ1V0DS00
PD17P228
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Data Sheet U14542EJ1V0DS00
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PD17P228
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics (France) S.A. NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583
NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829
J99.1
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Data Sheet U14542EJ1V0DS00
PD17P228
[MEMO]
Data Sheet U14542EJ1V0DS00
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PD17P228
SIMPLEHOST is a trademark of NEC Corporation.
Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of IBM Corporation.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
* The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.
M7 98.8

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